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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
RM0008
Table 17.
Port bit configuration table
Configuration mode
CNF1
CNF0
MODE1
MODE0
PxODR
register
General purpose
output
Alternate Function
output
Push-pull
Open-drain
Push-pull
Open-drain
0
1
0
1
0
1
01
10
11
see Table 18
0 or 1
0 or 1
don’t care
don’t care
Analog input
Input floating
0
0
1
don’t care
don’t care
Input
Input pull-down
Input pull-up
1
0
00
0
1
Table 18.
Output MODE bits
MODE[1:0]
00
01
10
11
Meaning
Reserved
Max. output speed 10 MHz
Max. output speed 2 MHz
Max. output speed 50 MHz
8.1.1
8.1.2
140/995
General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and the I/O ports are
configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b).
The JTAG pins are in input PU/PD after reset:
PA15: JTDI in PU
PA14: JTCK in PD
PA13: JTMS in PU
PB4: JNTRST in PU
When configured as output, the value written to the Output Data register (GPIOx_ODR) is
output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain
mode (only the N-MOS is activated when outputting 0).
The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every
APB2 clock cycle.
All GPIO pins have an internal weak pull-up and weak pull-down which can be activated or
not when configured as input.
Atomic bit set or reset
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify only one or several bits in a single atomic APB2 write
access. This is achieved by programming to ‘1’ the Bit Set/Reset Register (GPIOx_BSRR,
Doc ID 13902 Rev 9
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